********************************
* Copyright:                   *
* Vishay Intertechnology, Inc. *
********************************
*Nov 24, 2014
*ECN S14-2311, Rev. A
*File Name: Si3127DV_PS.txt and Si3127DV_PS.lib
*This document is intended as a SPICE modeling guideline and does not
*constitute a commercial product datasheet. Designers should refer to the
*appropriate datasheet of the same number for guaranteed specification
*limits.
.SUBCKT Si3127DV D G S 
M1 3 GX S S PMOS W= 1505255u L= 0.3u 
M2 S GX S D NMOS W= 1505255u L= 0.45u 
R1 D 3 6.043e-02 TC=6.121e-03,9.785e-06
CGS GX S 4.574e-10 
CGD GX D 1.911e-11 
RG G GY 9 
RTCV 100 S 1e6 TC=2.558e-04,5.547e-07
ETCV GY GX 100 200 1 
ITCV S 100 1u 
VTCV 200 S 1 
DBD D S DBD 1505255u 
**************************************************************** 
.MODEL PMOS PMOS ( LEVEL = 3 TOX = 5e-8 
+ RS = 0 KP = 2.398e-06 NSUB = 3.228e+16 
+ KAPPA = 6.432e-03 NFS = 4.77e+11 
+ LD = 0 IS = 0 TPG = -1    )
*************************************************************** 
.MODEL NMOS NMOS ( LEVEL = 3 TOX = 5e-8 
+NSUB = 1.421e+16 IS = 0 TPG = -1    )
**************************************************************** 
.MODEL DBD D ( 
+FC = 0.1 TT = 1.951e-07 T_measured = 25 BV = 61
+RS = 1.704e-02 N = 1.353e+00 IS = 2.616e-10 
+EG = 1.212e+00 XTI = 4.200e-01 TRS1 = 2.653e-03
+CJO = 1.093e-10 VJ = 1.036e+00 M = 5.441e-01 ) 
.ENDS 
